The present invention relates to a semiconductor memory device, and more specifically to an MOS-dRAM (MOS-dynamic random access memory) formed by integrating a plurality of memory cells each including an MOSFET and a memory capacitor.
In general, a MOS-dRAM uses memory cells which are each formed of a single MOSFET and a single memory capacitor. A MOS capacitor is conventionally used for the memory capacitor. The MOS-dRAM includes a memory array in which a plurality of memory cells is integrated into a matrix form on a semiconductor substrate. The memory array is provided with a plurality of word lines arranged along each column and a plurality of digit lines arranged along each row. The gates of the MOSFETs of a plurality of memory cells arranged along each word line are connected in common to the word line, while the drains of the MOSFETs of a plurality of memory cells arranged along each digit line are connected in common to the digit line.
Conventionally, the MOSFETs of the memory cells used in such a MOS-dRAM are n-channel, E-type MOSFETs. The memory capacitor is supplied at one end with a source supply voltage V.sub.SS (normally at zero volt) or drain supply voltage V.sub.DD (normally at 5 volts). In writing data in the memory capacitor to be stored therein from a digit line or in reading data stored in the memory capacitor onto the digit line, a selected word line is supplied with a voltage, e.g., at 7.5 volts, which is about 1.5 times as high as the drain supply voltage V.sub.DD. By doing this, the read or write efficiency of data stored in the form of electric charges in the memory capacitor is raised to 100 percent. If the voltage applied to the word line is equal to the drain supply voltage V.sub.DD, the potential at the node of the memory capacitor connected to the source of the MOSFET of the memory cell can be raised only up to V.sub.DD -Vth (Vth is the threshold voltage of MOSFET). Therefore, even if writing is executed with the drain supply voltage V.sub.DD applied to the digit line, the written voltage cannot become higher than V.sub.DD -Vth. In reading data stored in the memory capacitor onto the digit line, stored electric charges cannot be read out to 100 percent unless the word line is supplied with a sufficiently high voltage.
In reading or writing data, moreover, the variation of the conductance of the MOSFETs of the memory cells influences access time. If the voltage applied to the word line is increased, the conductance of the MOSFETs becomes greater, and the reading or writing speed is increased.
For these reasons, the voltage applied to the word line during an active period, in the prior art MOS-dRAM, is as high as about 7.5 volts.
The prior art MOS-dRAM, however, has the following problems. First, it takes time to pull up the voltage applied to the word line to be 1.5 times as high as the drain supply voltage V.sub.DD, resulting in longer access time. Namely, in a conventional clock generator using no pull-up circuit, the clock output rises up to the drain supply voltage V.sub.DD in a rise time of about 3 nsec. On the other hand, a clock generator adapted to drive the word lines is provided with a pull-up circuit. In this clock generator, therefore, a rise time of 10 nsec or more is needed for the clock output of 7.5 volts. Secondly, MOSFETs constituting the pull-up circuit are not perfectly reliable. In the MOSFETs used in this circuit, the drain-source voltage may sometimes exceed 7.5 volts, possibly causing punch-through or impact ionization attributed to intense electric fields near the drain. This leads to an increase in substrate current. Moreover, a number of hot carriers will be generated and injected into the gate oxide film of the MOSFETs to be trapped therein, causing fluctuations in the threshold voltage of the MOSFETs. To avoid these phenomena, it is necessary to use MOSFETs with a long channel length for the MOSFETs whose drain-source voltage is high. This leads to a third problem, that is, an increase in power consumption and in the space of the MOS-dRAM.
Besides the above problems, the MOSFETs of the memory cells are subject to the following drawbacks. For a higher degree of IC integration, it is basically necessary to reduce the size of elements constituting a circuit. In the MOS-dRAM, in particular, the channel length of the MOSFETs constituting the memory cells needs be shortened. It is generally known that as the channel length of the MOSFETs becomes shorter, what is called a short-channel effect is produced, lowering the threshold voltage. Thus, if the threshold voltage of the MOSFETs is lowered with the reduction of the channel length, the subthreshold current will increase, making the electric charges or information data stored in the memory capacitor liable to erasure. Conventionally, this problem is settled by increasing the surface impurity concentration of the channel regions of the MOSFETs of the memory cells by ion implantation to raise the threshold voltage of the MOSFETs. If the threshold voltage of the MOSFETs is increased, however, the aforesaid read or write efficiency can be improved only by further increasing the driving voltage for the word lines.
In the prior art MOS-dRAM, moreover, the potential of the nonselected word lines is adjusted to the source supply voltage V.sub.SS =0 volt. Thus, in the prior art device in which the threshold voltage of the MOSFETs of the memory cells is low, data stored in the memory cells could be erased by noise or capacitive coupling between the selected word line and nonselected word lines.